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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9852 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 cmos 300 mhz complete-dds functional block diagram phase/offset modulation inv. sinc filter sine-to-amplitude converter phase accumulator frequency accumulator 14-bit phase offset/ modulation 48-bit frequency tuning word frequency tuning word/phase word multiplexer and ramp start stop logic ramp-up/-down clock/logic and multiplexer 12-bit data programmable rate and update clocks 12 12 12 comparator amplitude modulation data 12-bit control dac programming registers 4 3 C20 3 ref clk multi- plexer ad9852 diff/single select reference clock in fsk/bpsk/hold data in bidirectional i/o update read write serial/parallel select 6-bit address or serial programming lines 8-bit parallel load master reset +v s gnd clock out analog in shaped on/off keying analog out dac r set analog out 300mhz dds i q digital multiplier 12-bit dds dac i/o port buffers features 300 mhz internal clock rate integrated 12-bit output dacs ultrahigh-speed, 3 ps rms jitter comparator excellent dynamic performance: 80 db sfdr @ 100 mhz ( 6 1 mhz) a out 4 3 to 20 3 programmable reference clock multiplier dual 48-bit programmable frequency registers dual 14-bit programmable phase offset registers 12-bit amplitude modulation and programmable shaped on/off keying function single pin fsk and psk data interface linear or nonlinear fm chirp functions with single pin frequency hold function frequency-ramped fsk <25 ps rms total jitter in clock generator mode automatic bidirectional frequency sweeping sin(x)/x correction simpli?ed control interface 10 mhz serial, 2-wire or 3-wire spi-compatible or 100 mhz parallel 8-bit programming 3.3 v single supply multiple power-down functions single-ended or differential input reference clock small 80-lead lqfp packaging applications agile, l.o. frequency synthesis programmable clock generator fm chirp source for radar and scanning systems test and measurement equipment commercial and amateur rf exciter general description the ad9852 digital synthesizer is a highly integrated device that uses advanced dds technology, coupled with an internal high-speed, high-performance d/a converters and a comparator to form a digitally-programmable agile synthesizer function. when referenced to an accurate clock source, the ad9852 generates a highly stable, frequency-phase amplitude-programmable sine wave output that can be used as an agile l.o. in communications, radar, and many other applications. the ad9852s innovative high-speed dds core provides 48-bit frequency resolution (1 microhertz tuning steps). phase truncation to 17 bits assures excellent sfdr. the ad9852s c ircuit architecture allows the ( continued on page 13)
C2C rev. 0 ad9852Cspecifications (v s = 3.3 v 6 5%, r set = 3.9 k v external reference clock frequency = 30 mhz with refclk multiplier enabled at 10 3 for ad9852asq, external reference clock frequency = 20 mhz with refclk multiplier enabled at 10 3 for ad9852ast, unless otherwise noted.) test ad9852asq ad9852ast parameter temp level min typ max min typ max unit ref clock input characteristics 1 internal clock frequency range full vi 5 300 5 200 mhz external ref clock frequency range refclk multiplier enabled full vi 5 75 5 50 mhz refclk multiplier disabled full vi 5 300 5 200 mhz duty cycle 25 c v 50 50 % input capacitance 25 civ 3 3 pf input impedance 25 c iv 100 100 k w differential mode common-mode voltage range minimum signal amplitude 25 c iv 800 800 mv p-p common-mode range 25 c iv 1.6 1.75 1.9 1.6 1.75 1.9 v v ih (single-ended mode) 25 c iv 2.3 2.3 v v il (single-ended mode) 25 civ 1 1 v dac static output characteristics output update speed full i 300 200 msps resolution 25 c iv 12 12 bits sine and aux. dac full-scale output current 25 c iv 5 10 20 5 10 20 ma gain error 25 c i C6 +2.25 C6 +2.25 % fs output offset 25 ci 2 2 m a differential nonlinearity 25 c i 0.3 1.25 0.3 1.25 lsb integral nonlinearity 25 c i 0.6 1.66 1 1.66 lsb output impedance 25 c i 100 100 k w voltage compliance range 25 c i C0.5 +1.0 C0.5 +1.0 v dac wideband sfdr 1 mhz to 20 mhz a out 25 c v 58 58 dbc 20 mhz to 40 mhz a out 25 c v 56 56 dbc 40 mhz to 60 mhz a out 25 c v 52 52 dbc 60 mhz to 80 mhz a out 25 c v 48 48 dbc 80 mhz to 100 mhz a out 25 c v 48 48 dbc 100 mhz to 120 mhz a out 25 c v 50 dbc dac narrowband sfdr 10 mhz a out ( 1 mhz) 25 c v 83 83 dbc 10 mhz a out ( 250 khz) 25 c v 83 83 dbc 10 mhz a out ( 50 khz) 25 c v 91 91 dbc 41 mhz a out ( 1 mhz) 25 c v 82 82 dbc 41 mhz a out ( 250 khz) 25 c v 84 84 dbc 41 mhz a out ( 50 khz) 25 c v 89 89 dbc 119 mhz a out ( 1 mhz) 25 c v 71 71 dbc 119 mhz a out ( 250 khz) 25 c v 77 77 dbc 119 mhz a out ( 50 khz) 25 c v 83 83 dbc residual phase noise (a out = 5 mhz, ext. clk = 30 mhz, refclk multiplier engaged at 10 ) 1 khz offset 25 c v 140 140 dbc/hz 10 khz offset 25 c v 138 138 dbc/hz 100 khz offset 25 c v 142 142 dbc/hz (a out = 5 mhz, ext. clk = 300 mhz, refclk multiplier bypassed) 1 khz offset 25 c v 142 142 dbc/hz 10 khz offset 25 c v 148 148 dbc/hz 100 khz offset 25 c v 152 152 dbc/hz pipeline delays phase accumulator and dds core 25 c iv 17 17 sysclk cycles inverse sinc filter 25 c iv 12 12 sysclk cycles digital multiplier 25 c iv 10 10 sysclk cycles
C3C rev. 0 ad9852 test ad9852asq ad9852ast parameter temp level min typ max min typ max unit master reset duration 25 c iv 10 10 sysclk cycles comparator input characteristics input capacitance 25 cv 3 3 pf input resistance 25 c iv 500 500 1k w input current 25 ci 1 5 1 5 m a hysteresis 25 c iv 10 20 10 20 mv p-p comparator output characteristics logic 1 voltage, high z load full vi 3.10 3.10 v logic 0 voltage, high z load full vi 0.16 0.16 v output power, 50 w load, 120 mhz toggle rate 25 c i 9 11 9 11 dbm propagation delay 25 civ 3 3 ns output duty cycle error 2 25 ci C10 1 +10 C10 1 +10 % rise/fall time, 5 pf load 25 cv 2 2 ns toggle rate, high z load 25 c iv 300 350 300 350 mhz toggle rate, 50 w load 25 c iv 375 400 375 400 mhz output cycle-to-cycle jitter 3 25 c iv 3 3 ps rms comparator narrowband sfdr 4 10 mhz ( 1 mhz) 25 c v 84 84 dbc 10 mhz ( 250 khz) 25 c v 84 84 dbc 10 mhz ( 50 khz) 25 c v 92 92 dbc 41 mhz ( 1 mhz) 25 c v 76 76 dbc 41 mhz ( 250 khz) 25 c v 82 82 dbc 41 mhz ( 50 khz) 25 c v 89 89 dbc 119 mhz ( 1 mhz) 25 c v 73 73 dbc 119 mhz ( 250 khz) 25 c v 73 73 dbc 119 mhz ( 50 khz) 25 c v 83 83 dbc clock generator output jitter 4 5 mhz a out 25 c v 23 23 ps rms 40 mhz a out 25 c v 12 12 ps rms 100 mhz a out 25 c v 7 7 ps rms parallel i/o timing characteristics t asu (address setup time to wr signal active) full iv 4 4 ns t adhw (address hold time to wr signal inactive) full iv 3 3 ns t dsu (data setup time to wr signal inactive) full iv 2 2 ns t dhd (data hold time to wr signal inactive) full iv 0 0 ns t wrlow ( wr signal minimum low time) full iv 3 3 ns t wrhigh ( wr signal minimum high time) full iv 7 7 ns t wr ( wr signal minimum period) full iv 10 10 ns t adv (address to data valid time) full v 15 15 15 15 ns t adhr (address hold time to rd signal inactive) full iv 5 5 ns t rdlov ( rd low-to-output valid) full iv 15 15 ns t rdhoz ( rd high-to-data three-state) full iv 10 10 ns serial i/o timing characteristics t pre ( cs setup time) full iv 30 30 ns t sclk (period of serial data clock) full iv 100 100 ns t dsu (serial data setup time) full iv 30 30 ns t sclkpwh (serial data clock pulsewidth high) full iv 40 40 ns t sclkpwl (serial data clock pulsewidth low) full iv 40 40 ns t dhld (serial data hold time) full iv 0 0 ns t dv (data valid time) full v 30 30 ns cmos logic inputs logic 1 voltage 25 c i 2.7 2.7 v logic 0 voltage 25 c i 0.4 0.4 v logic 1 current 25 civ 5 5 m a logic 0 current 25 civ 5 5 m a input capacitance 25 cv 3 3 pf
C4C rev. 0 ad9852Cspecifications caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9852 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device test ad9852asq ad9852ast parameter temp level min typ max min typ max unit power supply 5 +v s current 6 25 c i 815 922 585 660 ma +v s current 7 25 c i 640 725 465 520 ma +v s current 8 25 c i 585 660 425 475 ma p diss 6 25 c i 2.7 3.195 1.93 2.385 w p diss 7 25 c i 2.115 2.515 1.53 1.805 w p diss 8 25 c i 1.930 2.285 1.400 1.650 w p diss power-down mode 25 c i 50 50 mw notes 1 the reference clock inputs are con?gured to accept a 1 v p-p (minimum) dc offset sine wave centered at one-half the applied v dd or a 3 v ttl-level pulse input. 2 change in duty cycle from 1 mhz to 100 mhz with 1 v p-p sine wave input and 0.5 v threshold. 3 represents comparators inherent cycle-to-cycle jitter contribution. input signal is a 1 v, 40 mhz square wave. measurement dev ice wavecrest dts C 2075. 4 comparator input originates from analog out section via external 7-pole elliptic lpf. single-ended input, 0.5 v p-p. comparator output terminated in 50 w . 5 important: in the 80-lead lqfp package simultaneous operation at the maximum ambient temperature of 85 c and at the maximum internal clock frequency at 200 mhz may cause the maximum die junction temperature of 150 c to be exceeded. refer to the section of the data sheet entitled power dissipation section and thermal considerations section for derating and thermal management information. 6 all functions engaged. 7 all functions except inverse sinc engaged. 8 all functions except inverse sinc and digital multipliers engaged. speci?cations subject to change without notice. explanation of test levels test level i C 100% production tested. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C devices are 100% production tested at 25 c and guaranteed by design and characterization testing for industrial operating temperature range. absolute maximum ratings * maximum junction temperature . . . . . . . . . . . . . . . . 150 c v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . C0.7 v to +v s digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature . . . . . . . . . . . . . . . . . C40 c to +85 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . 300 c maximum clock frequency . . . . . . . . . . . . . . . . . . 300 mhz * absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. ordering guide model temperature range package description package option ad9852asq C40 c to +85 c thermally-enhanced 80-lead lqfp sq-80 ad9852ast C40 c to +85 c 80-lead lqfp st-80 ad9852/pcb 0 c to 70 c evaluation board
ad9852 C5C rev. 0 pin function descriptions pin no. pin name function 1C8 d7Cd0 eight-bit bidirectional parallel programming data inputs. used only in parallel programming mode. 9, 10, 23, dvdd connections for the digital circuitry supply voltage. nominally 3.3 v more positive than agnd 24, 25, 73, and dgnd. 74, 79, 80 11, 12, 26, dgnd connections for digital circuitry ground return. same potential as agnd. 27, 28, 72, 75, 76, 77, 78 13, 35, 57 nc no internal connection. 58, 63 14C19 a5Ca0 six-bit parallel address inputs for program registers. used only in parallel programming mode. a0, a1, and a2 have a second function when the serial programming mode is selected. see immediately below. (17) a2/io reset allows a reset of the serial communications bus that is unresponsive due to improper program- ming protocol. resetting the serial bus in this manner does not affect previous programming nor does it invoke the default programming values seen in the table v. active high. (18) a1/sdo unidirectional serial data output for use in 3-wire serial communication mode. (19) a0/sdio bidirectional serial data input/output for use in 2-wire serial communication mode. 20 i/o ud bidirectional frequency update signal. direction is selected in control register. if selected as an input, a rising edge will transfer the contents of the programming registers to the internal works of the ic for processing. if i/o ud is selected as an output, an output pulse (low to high) of eight system clock cycle duration indicates that an internal frequency update has occurred. 21 wrb/sclk write parallel data to programming registers. shared function with sclk. serial clock signal associated with the serial programming bus. data is registered on the rising edge. this pin is shared with wrb when the parallel mode is selected. 22 rdb/csb read parallel data from programming registers. shared function with csb. chip-select signal associated with the serial programming bus. active low. this pin is shared with rdb when the parallel mode is selected. 29 fsk/bpsk/ mu ltifunction pin according to the mode of operation selected in the programming control register. hold if in the fsk mode logic low selects f1, logic high selects f2. if in the bpsk mode, logic low selects phase 1, logic high selects phase 2. if in the chirp mode, logic high engages the hold function causing the frequency accumulator to halt at its current location. to resume or commence chirp, logic low is asserted. 30 shaped must first be selected in the programming control register to function. a logic high will cause the keying cosine dac output to ramp-up from zero-scale to full-scale amplitude at a preprogrammed rate. logic low causes the full-scale output to ramp-down to zero-scale at the preprogrammed rate. 31, 32, 37 avdd connections for the analog circuitry supply voltage. nominally 3.3 v more positive than agnd 38, 44, 50, and dgnd. 54, 60, 65 33, 34, 39, agnd connections for analog circuitry ground return. same potential as dgnd. 40, 41, 45, 46, 47, 53, 59, 62, 66, 67 36 vout internal high-speed comparators noninverted output pin. designed to drive 10 dbm to 50 w load as well as standard cmos logic levels. 42 vinp voltage input positive. the internal high-speed comparators noninverting input. 43 vinn voltage input negative. the internal high-speed comparators inverting input. 48 iout1 unipolar current output of the cosine dac. 49 iout1b complementary unipolar current output of the cosine dac. 51 iout2b complementary unipolar current output of the auxiliary dac. 52 iout2 unipolar current output of the auxiliary dac.
ad9852 C6C rev. 0 pin no. pin name function 55 dacbp common bypass capacitor connection for both dacs. a 0.01 m f chip cap from this pin to avdd improves harmonic distortion and sfdr slightly. no connect is permissible (slight sfdr degradation). 56 dac r set common connection for both dacs to set the full-scale output current. r set = 39.9/i out . normal r set range is from 8 k w (5 ma) to 2 k w (20 ma). 61 pll filter this pin provides the connection for the external zero compensation network of the refclk multipliers pll loop ?lter. the zero compensation network consists of a 1.3 k w resistor in series with a 0.01 m f capacitor. the other side of the network should be co nnected to avdd as close as possible to pin 60. for optimum phase n oise performance, the refclk multiplier can be bypassed by setting the bypass pll bit in control register 1e. 64 diff clk differential refclk enable. a high level of this pin enables the differential clock inputs, refclk and refclkb enable (pins 69 and 68 respectively). the minimum differential signal amplitude required is 800 mv p-p. the centerpoint or common-mode range of the differential signal ranges from 1.6 v to 1.9 v. 68 refclkb the complementary (180 degrees out-of-phase) differential clock signal. user should tie this pin high or low when single-ended clock mode is selected. same signal levels as refclk. 69 refclk s ingle-ended reference clock input or one of two differential clock signals. normal 3.3 v cmos logic levels or 1 v p-p sine wave centered about 1.6 v. 70 s/p select selects between serial programming mode (logic low) and parallel programming mode (logic high). 71 master initializes the serial/parallel programming bus to prepare for user programming; sets programming reset registers to a do-nothing state de?ned by the default values seen in the table v. active on logic high. asserting master reset is essential for proper operation upon power-up.
ad9852 C7C rev. 0 pin configuration pin 1 identifier top view (not to scale) ad9852 80-pin lqfp 14 3 14 3 1.4 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 40 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 d7 d6 d5 d4 d3 d2 d1 d0 dvdd dvdd dgnd dgnd nc a5 a4 a3 a2/io reset a1/sdo a0/sdio i/o ud wrb/sclk rdb/csb dvdd dvdd dvdd dgnd dgnd dgnd fsk/bpsk/hold shaped keying avdd avdd agnd agnd nc vout avdd avdd agnd agnd agnd vinp vinn avdd agnd agnd agnd iout1 iout1b avdd iout2b iout2 agnd avdd dacbp dac r set nc nc agnd avdd pll filter agnd nc diff clk enable avdd agnd agnd refclockb refclock s/p select master reset dgnd dvdd dvdd dgnd dgnd dgnd dgnd dvdd dvdd nc = no connect figure 1. equivalent input and output circuits a. dac outputs b. comparator output c. comparator input d. digital input v dd i out i outb v dd vinp/ vinn v dd digital in digital out v dd
ad9852 C8C rev. 0 0 start 0hz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 15mhz/ stop 150mhz figure 2. wideband sfdr, 19.1 mhz 0 start 0hz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 15mhz/ stop 150mhz figure 3. wideband sfdr, 39.1 mhz 0 start 0hz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 15mhz/ stop 150mhz figure 4. wideband sfdr, 59.1 mhz 0 start 0hz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 15mhz/ stop 150mhz figure 5. wideband sfdr, 79.1 mhz 0 start 0hz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 15mhz/ stop 150mhz figure 6. wideband sfdr, 99.1 mhz 0 start 0hz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 15mhz/ stop 150mhz figure 7. wideband sfdr, 119.1 mhz figures 2C7 indicate the wideband harmonic distortion performance of the ad9852 from 19.1 mhz to 119.1 mhz fundamen- tal output, reference clock = 30 mhz, refclk m ultiplier = 10. each graph plotted from 0 mhz to 150 mhz.
ad9852 C9C rev. 0 figures 8C11 show the tr adeoff in elevated noise floor, increased phase noise, and occasional discrete sp urious energy when the internal refclk multiplier circuit is engaged. plots with wide (1 mhz) and narrow (50 khz) spans are shown. 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 100khz/ span 1mhz figure 10. narrowband sfdr, 39.1 mhz, 1 mhz bw, 30 mhz extclk with refclk multiply = 10 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 5khz/ span 50khz figure 11. narrowband sfdr, 39.1 mhz, 50 khz bw, 30 mhz extclk/refclk multiplier = 10 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 5khz/ span 50khz figure 12. narrowband sfdr, 39.1 mhz, 50 khz bw, 100 mhz extclk with refclk multiplier bypassed 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 100khz/ span 1mhz figure 8. narrowband sfdr, 39.1 mhz, 1 mhz bw, 300 mhz extclk with refclk multiply bypassed 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 5khz/ span 50khz figure 9. narrowband sfdr, 39.1 mhz, 50 khz bw, 300 mhz extclk with refclk multiplier bypassed figures 12 and 13 show the slight increase in noise floor both with and without the pll when slower clock speeds are used to generate the same fundamental frequency, that is, with a 100 mhz clock as opposed to a 300 mhz clock in figures 9 and 11. 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 5khz/ span 50khz figure 13. narrowband sfdr, 39.1 mhz, 50 khz bw, 10 mhz extclk with refclk multiplier = 10
ad9852 C10C rev. 0 figures 14 and 15 show the effects of utilizing sweet spots in the tuning range of a dds. figure 14 represents a tuning word that accentuates the aberrations associated with truncation in the dds algorithm. figure 15 is essentially the same output frequency (a few tuning codes over), but it displays much fewer spurs on the output due to the selection of a tuning sweet spot. consideration should be given to all dds applications to exploit the bene?t of sweet spot tuning. 0 center 112.499mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 50khz/ span 500khz figure 14. the opposite of a sweet spot. 11 2.469 mhz with multiple high energy spurs close around the fundamental. 0 center 112.469mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 50khz/ span 500khz figure 15. a slight change in tuning word yields dramatically better results. 112.499 mhz with all spurs shifted out-of-band. figures 16 and 17 show the narrowband performance of the ad 9852 when operating with a 20 mhz reference clock and the refclk multiplier enabled at 10 vs. a 200 mhz external reference clock. 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 5khz/ span 50khz figure 16. narrowband sfdr, 39.1 mhz, 50 khz bw, 200 mhz extclk with refclk multiplier bypassed 0 center 39.1mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 5khz/ span 50khz figure 17. narrowband sfdr, 39.1 mhz, 50 khz bw, 10 mhz extclk with refclk multiplier = 10
ad9852 C11C rev. 0 dac current C ma 55 0 sfdr C dbc 54 53 52 51 50 49 48 5 10152025 figure 19. sfdr vs. dac current, 59.1 mhz a out , 300 mhz extclk frequency C mhz 620 0 supply current C ma 615 610 605 600 595 590 20 40 60 80 100 120 140 figure 20. supply current vs. output frequency; variation is minimal as a percentage and heavily dependent on tuning word frequency C hz C110 100 phase noise C dbc/hz C115 C120 C125 C130 C135 C140 C145 C150 C155 1k 10k 100k 80mhz 5mhz a. residual phase noise 300 mhz direct clocking frequency C hz C110 100 phase noise C dbc/hz C115 C120 C125 C130 C135 C140 C145 C150 C155 1k 10k 100k 80mhz 5mhz b. residual phase noise, 300 mhz (10 refclk multiplier enabled) figure 18. residual phase noise, extclk = 300 mhz, refclk multiplier disabled/enabled at 10 rise time 1.04ns 500ps/div 232mv/div 50 v input jitter [10.6ps rms] C33ps 0ps +33ps figure 21. typical comparator output jitter, 40 mhz a out , 300 mhz extclk/refclk multiplier disabled ref1 rise 1.174ns c1 fall 1.286ns ch1 500mv v m 500ps ch1 980mv figure 22. comparator rise/fall times
ad9852 C12C rev. 0 frequency C mhz 1200 0 amplitude C mv p-p 1000 800 600 400 200 0 100 200 300 400 500 minimum comparator input drive v cm = 0.5v figure 23. comparator toggle voltage requirement i q rx rf in dual 8-/10-bit adc digital demodulator rx baseband digital data out 8 8 i/q mixer and low-pass filter vca adc encode adc clock frequency locked to tx chip/ symbol/pn rate reference clock 48 chip/symbol/pn rate data ad9852 clock generator figure 25. chip rate generator in spread spectrum application 50 v bandpass filter 50 v i out ad9852 fundamental f c C f o image f clk f c + f o image bandpass filter f c + f o image ad9852 spectrum final output spectrum figure 26. using an aliased image to generate a high frequency vco loop filter phase comparator reference clock filter ad9852 dds tuning word ref clk in rf frequency out dac out figure 27. programmable divide-by-n synthesizer lpf refclk rf/if input ad9852 baseband sin figure 24. synthesized l.o. application for the ad9852
ad9852 C13C rev. 0 tuning word vco loop filter phase comparator ref clock rf frequency out filter ad9852 dds divide-by-n figure 28. agile high-frequency synthesizer m processor/ controller fpga, etc. r set 8-bit parallel or serial programming data and control signals ad9852 cmos logic "clock" out reference clock 300mhz max direct mode or 15 to 75mhz max in the 4 3 -20 3 clock multiplier mode 2k v control "i" dac 1 2 notes: i out = approx 20ma max when r set = 2k v switch postion 1 provides complementary sinusoidal signals to the comparator to produce a fixed 50% output duty cycle from the comparator. switch postion 2 provides a user programmable dc threshold voltage to allow setting of the comparator output duty cycle. low-pass filter low-pass filter + figure 30. frequency agile clock generator applications for the ad9852 (continued from page 1) generation of a sine output at frequencies up to 150 mhz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. the (externally ?ltered) sine wave output can be converted to a square wave by the internal comparator for agile clock generator applications. the device provides 14 bits of digitally-controlled phase modulation and single-pin psk. the on-board 12 -bit d ac, coupled with the inno vative dds architecture, provide excellent wideband and narrowband out- put sfdr. there is also an auxiliary dac that can be con?gured as a user-programmable control dac. when con?gured with the on-board comparator, the 12-bit control dac facilitates duty cycle control, in the high-speed clock generator application. a 12-bit digital multiplier permits programm able amplitude modu- lation, shaped on/off keying and precise amplitude control of the output. chirp f unctionality is also inclu ded wh ich facilitates wide bandwidth frequency sweeping applications. the ad9852s programmable 4 C20 refclk multiplier circuit generates the 300 mhz clock internally from a lower frequency external reference clock. this saves the user the expense and dif?culty of implementing a 300 mhz clock source. direct 300 mhz clocking is also accommodated with either single-ended or differential inputs. single-pin conventional fsk and the enhanced sp ectral qualities of ramped fsk are supported. the ad9852 uses advanced 0.35 micron cmos technology to provide this high level of functionality on a single 3.3 v supply. the ad9852 is available in a space-saving 80-lead lqfp surface-mount package and a thermally-enhanced 80-lead lqfp package. the ad9852 is pin-for-pin compatible with the ad9854 quadrature output synthesizer device. it is speci?ed to operate over the extended industrial temperature range of C40 c to +85 c. overview the ad9852 digital synthesizer is a highly flexible device that will address a wide range of applications. the device consists of an nco with 48-bit phase accumulator, programmable ref- erence clock multiplier, inverse sinc ?lters, digital multipliers, two 12-bit/300 mhz dacs, high-speed ana log comparator, and interface logic. this highly integrated d evice can be con?g- ured to serve as a synthesized l.o., agile clock generator, and fsk/bpsk modulator. the theory of operation of the func- tional blocks of the device, and a technical description of the signal flow through a dds device, can be found in a tutorial from analog devices, called, a technical t utorial on digital signal synthesis. this tutorial is available on cd-rom and information on obtaining it can be found at the analog devices dds website at www.analog.com/dds . the tutorial also provides basic applications information for a variety of digital synthesis implementations. the dds background subject matter is not covered in this data sheet; the functions and features of the ad9852 will be individually discussed herein. reference clock 50 v 1:1 transformer i.e. mini-circuits t1C1t filter 50 v differential transformer-coupled output ad9852 dds i out i out figure 29. differential output connection for reduction of common-mode signals
ad9852 C14C rev. 0 using the ad9852 internal and external update clock this function is comprised of a bidirectional i/o pin, pin 20, and a programmable 32-bit down-counter. in order for programming changes to be transferred from the i/o buffer registers to the active core of the dds, a clock signal (low-to-high edge) must be externally supplied to pin 20 or internally generated by the 32-bit update clock. an externally generated update clock is internally synchronized with the system clock to prevent partial transfer of program register information due to violation of data setup or hold times. this mode gives the user complete control of when updated program information becomes effective. the default mode is set for internal update clock (int update clk control register bit is logic high). to switch to external update clock mode, the int update clk register bit must be set to logic low. the internal update mode generates automatic, periodic update pulses whose time period is set by the user. an internally generated update clock can be established by programming the 32-bit update clock registers (address 16C19 hex) and setting the int update clk (address 1f hex) control register bit to logic high. the update clock down-counter function operates at the system clock/2 (150 mhz maximum) and counts down from a 32-bit binary value (programmed by the user). when the count reaches 0, an automatic i/o update of the dds output or functions is generated. the update clock is routed internally and externally on pin 20 to allow users to synchronize programming of update information with the update clock rate. the time period between update pulses is given as: (n+1) (system clock period 2) where n is the 32-bit value programmed by the user. allow- able range of n is from 1 to (2 32 C1). the internally generated update pulse output on pin 20 has a ?xed high time of eight system clock cycles. shaped on/off keying allows user to control the ramp-up and ramp-down time of an on/off emission from the i and q dacs. this function is used in burst transmissions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. users must ?rst enable the digital multipliers by setting the osk en bit (con- trol r egister address 20 hex) to logic high in the control register. otherwise, if the osk en bit is set low, the digital multipliers responsible for amplitude control are bypassed and the i and q dac outputs are set to full-scale amplitude. in addition to setting the osk en bit, a second control bit, osk int (also at address 20 hex) must be set to logic high. logic high selects the linear internal control of the output ramp-up or ramp-down function. a logic low in the osk int bit switches control of abrupt on/off keying shaped on/off keying figure 31. shaped on/off keying the digital multipliers to user programmable 12-bit registers allowing users to dynamically shape the amplitude transition in practically any fashion. these 12-bit registers, labeled out- put shape key are located at addresses 21 through 24 hex in table v. the m aximum output amplitude is a function of the r set resistor and is not programmable when osk int is enabled. next, the transition time from zero-scale to full-scale must be programmed. the tra nsition time is a function of two ?xed elements and one variable. the variable element is the program mable 8-bit ramp rate counter . this is a down-counter being clocked at the system clock rate (300 mhz max) that outputs one pulse whenever the counter reaches zero. this pulse is routed to a 12-bit counter that increments one lsb for every pulse received. the outputs of the 12-bit counter are connected to the 12-bit digital multiplier. when the digital multiplier has a value of all zeros at its inputs, the input signal is multiplied by zero, producing zero-scale. when the multiplier has a value of all ones, the input signal is multiplied by a value of one, producing full-scale. there are 4094 remaining fractional multiplier values that will produce output amplitudes corresponding to their binary values. 12-bit digital multiplier 12 12 (bypass multiplier) osk en = 0 osk en = 1 osk en = 0 osk en = 1 12 12 digital signal in user programmable 12-bit q-channel multiplier "output shape key q mult" register 12 osk en = 1 osk en = 0 12-bit counter 1 8-bit down- counter system clock shaping keying pin sine dac figure 32. block diagram of data pathway of the digital multiplier sect ion responsible for shaped keying function the two ?xed elements are the clock period of the system clock, which drives the ramp rate counter, and the 4096 amplitude steps between zero-scale and full-scale. to give an exam ple, assume that the system clock of the ad9852 is 100 mhz (10 ns period). if the ramp rate counter is programmed for a minimum count of five, it will take two system clock periods (one rising edge loads the count-down value, the next edge decrements the counter from five to four). the relationship of the 8-bit count- down value to the time period between output pulses is given as: (n+1) system clock period , where n is the 8-bit count-down value. it will take 4096 of these pulses to a dvance the 12-bit up-counter from zero-scale to full- scale. therefore, the minimum shaped keying ramp time for a 100 mhz system clock is 4096 6 10 ns = approximately 246 m s. the maximum ramp time w ill be 4096 256 10 ns = approximately 10.5 m s.
ad9852 C15C rev. 0 finally, changing the logic state of pin 30, shaped keying will automatically perform the programmed output envelope functions when osk int is high. a logic high on pin 30 causes the out- puts to linearly ramp up to full-scale amplitude and hold until the logic level is changed to low, causing the outputs to ramp down to zero-scale. cosine dac the cosine dac generates the 300 msps (maximum) cosine output of the dds. the maximum output amplitude is set by the dac r set resistor at pin 56. this is a current-out dac with a full-scale maximum output of 20 ma; however, a nomi- nal 10 ma output current provides best spurious-free dy namic range (s fdr) performance. the value of r set = 39.93/i out , where i out is in amps. dac output compliance speci?cation lim- its the maximum voltage developed at the outputs to C0.5 v to +1 v. voltages developed beyond this limitation will cause exces- sive dac distortion and possibly permanent da mage. the user must choose a proper load impedance to limit the output voltage swing to the compliance limits. for best sfdr, both dac outputs should be terminated equally, es pecially at higher output fre- quencies where harmonic distortion errors are more prominent. the cosine dac is preceded by inverse sin(x)/x ?lters (a.k.a. inverse sinc ?lter) that precompensate for dac output amplitude variations over frequency to achieve flat amplitude response from dc to nyquist. a digital multiplier follows the inverse sinc ?lters to allow amplitude control, amplitude modulation and ampli- tude shaped keying. the inverse sinc ?lter (address 20 hex, bypass inv sinc bit)) and digital multiplier (address 20 hex, osk en bit) can be bypassed for power conservation by setting those bits high. both dacs can be powered down by setting the dac pd bit high (address 1d of control register) when not needed. cosine dac outputs are designated as iout1 and iout1b, pins 48 and 49 respectively. control dac the 12-bit auxiliary, or control dac can provide dc control levels to external circuitry, generate ac signals, or duty cycle con- trol, of the on-b oard comparator. the input twos complement data is channeled through the serial or parallel interface to the 12-bit register (address 26 and 27 hex) at a maximum 100 mhz data rate. this dac is clocked at the system clock, 300 msps (maximum), and has the same maximum output current capa- bility as that of the cosine dac. the single r set resistor on the ad9852 sets the full-scale out put current for both cosine dac and the control dacs. the control dac can be separately powered down for power conservation when not needed by setting the control dac power-down bit high (address 1d hex). control dac outputs are designated as iout2 and iout2b (pins 52 and 51 respectively). 0 center 50mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 10mhz/ span 100mhz images fundamental output power decreases with increasing frequency figure 33. normal sin(x)/x dac output power envelope filter 0 center 50mhz C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 10mhz/ span 100mhz fundamental output power is "flat" from dc to 1/2 fclk figure 34. inverse sin(x)/x (inverse sinc) filter engaged inverse sinc function this ?lter precompensates input data to the cosine dac for the sin (x)/x roll-off function to allow wide bandwidth signals (such as qpsk) to be output from the dacs without appreciable amplitude variations that will cause increased evm (error vector magnitude). the inverse sinc function may be bypassed to signi?cantly reduce power consumption, especially at higher clock speeds. inverse sinc is engaged by default and is bypassed by bringing the bypass inv sinc bit high in control register 20 (hex) in table v. refclk multiplier this is a programmable pll-based reference clock multiplier that allows the user to select an integer clock multiplying value over the range of 4 to 20 by which the refclk input will be multiplied. use of this function allows users to input as little as 15 mhz to produce a 300 mhz internal system clock . five bits in control register 1e hex set the multiplier value as follows in table i.
ad9852 C16C rev. 0 table i. refclk multiplier control register values multiplier value ref mult 4 ref mult 3 ref mult 2 ref mult 1 ref mult 0 400100 500101 600110 700111 801000 901001 1001010 1101011 1201100 1301101 1401110 1501111 1610000 1710001 1810010 1910011 2010100 the refclk multiplier function can be bypassed to allow direct clocking of the ad9852 from an external clock source. the system clock for the ad9852 is either the output of the refclk multiplier (if it is engaged) or the refclk inputs. refclk may be either a single-ended or differential input by setting pin 64, diff clk enable , low or high respectively. pll range bit the pll range bit selects the frequency range of the refclk multiplier pll. for operation from 200 mhz to 300 mhz (internal system clock rate) the pll range bit should be set to logic 1. for operation below 200 mhz, the pll range bit should be set to logic 0. the pll range bit adjusts the pll loop parameters for optimized phase noise performance within each range. pin 61, pll filter this pin provides the connection for the external zero compen- sation network of the pll loop ?lter. the zero compensation network consists of a 1.3 k w resistor in series with a 0.01 m f capacitor. the other side of the network should be connected to as close as possible to pin 60, avdd. for optimum phase noise performance the clock multiplier can be bypassed by setting the bypass pll bit in control register address 1e. differential refclk enable a high level on this pin enables the differential clock inputs, refclock and refclockb (pins 69 and 68 respec- tively). the minimum differential signal amplitude required is 800 mv p-p. the centerpoint or common-mode range of the differential signal can range from 1.6 v to 1.9 v. when pin 64 ( diff clk enable ) is tied low, refclk (pin 69) is the only active clock input. this is referred to as the single-ended mode. in this mode, pin 68 (refclkb) should be tied low or high, but not left floating. parallel/ serial programming mode setting pin 70 high invokes parallel mode, whereas setting pin 70 low will invoke the serial programming mode. please refer to the text describing the serial and parallel programming protocol contained in this data sheet for further information. two control bits located at address 20 hex in the table v apply only to the serial programming mode. lsb first when high, dictates that serial data will be loaded starting with the lsb of the word. when low (the default value), serial data is loaded starting with the msb of the word. sdo active when high indicates that the sdo pin, pin 18, is dedicated to reading back data from the ad9852 registers. when sdo active is low (default value), this indicates that the sdio pin, pin 19, acts as a bidirectional serial data input and output pin and pin 18 has no function in the serial mode. description of ad9852 modes of operation there are ?ve programmable modes of operation of the ad9852. selecting a mode requires that three bits in the control register (parallel address 1f hex) be programmed as follows in table ii. table ii. mode selection table mode 2 mode 1 mode 0 result 0 0 0 single-tone 0 0 1 fsk 0 1 0 ramped fsk 0 1 1 chirp 1 0 0 bpsk in each mode, engaging certain functions may or may not be permitted. shown in table iii is a listing of some important functions and their availability for each mode.
ad9852 C17C rev. 0 single-tone (mode 000) this is the default mode when master reset is asserted or when it is user-programmed into the control register. the phase accumulator, responsible for generating an output frequency, is presented with a 48-bit value from frequency tuning word 1 registers whose default values are zero. default values from the remaining applicable registers will further de?ne the single-tone output signal qualities. the default values after a master reset, de?ne a safe, no output value resulting in an output signal of 0 hertz, 0 phase. upon power-up and reset the output from both i and q dacs will be a dc value equal to the midscale output current. this is the default mode amplitude setting of zero. refer to the digital multi- plier s ection for further explana tion of the output am plitude control. it will be necessary to program all or some of the 28 program registers to realize a user-de?ned output signal. figure 35 graphically shows the transition from the default con- dition (0 hz) to a user-de?ned output frequency (f1). as with all analog devices ddss, the value of the frequency tuning w ord is determined using the following equation: ftw = (desired output frequency 2 n )/sysclk. 000 (single tone) mode f1 tw1 000 (default) 0 f1 0 frequency figure 35. default state to user-de?ned output transition where n is the phase accumulator resolution (48 bits in this instan ce), frequency is expressed in hertz, and the ftw, frequ ency t uning word, is a decimal number. once a decimal number has been calculated, it must be rounded to an integer and then converted to binary formata series of 48 binary- weighted 1s or 0s. the fundamental sine wave dac output frequency range is from dc to 1/2 sysclk. changes in frequency are phase continuousthat is, the new frequency uses the last phase of the old frequency as the reference point to compute the ?rst new frequency phase. the single-tone mode allows the user to control the following signal qualities: ? output frequency to 48-bit accuracy ? output amplitude to 12-bit accuracy C fixed, user-de?ned, amplitude control C variable, programmable amplitude control C automatic, programmable, single- pin-controlled, shaped on/off keying ? output phase to 14-bit accuracy furthermore, all of these qualities can be changed or modulated via the 8-bit parallel programming port at a 100 mhz parallel-byte rate, or at a 10 mhz serial rate. incorporating this attribute will permit fm, am, pm, fsk, psk, ask operation in the single- tone mode. table iii. function availability vs. mode of operation single-pin single-pin phase amplitude inverse frequency frequency automatic phase phase fsk/bpsk shaped- offset or control or sinc tuning tuning frequency mode adjust 1 adjust 2 or hold keying modulation modulation filter word 1 word 2 sweep single-tone 3 xx 33 3 33 xx fsk 3 x 33 3 3 333 x ramped fsk 3 x 3 3 3 3 3333 chirp 3 x 33 3 3 33 x 3 bpsk 333 3 x 333 xx
ad9852 C18C rev. 0 unramped fsk (mode 001) when selected, the output frequency of the dds is a function of the values loaded into frequency tuning word registers 1 and 2 and the logic level of pin 29 (fsk/bpsk/hold). a logic low on pin 29 chooses f1 (frequency tuning word 1, parallel address 4C9 hex) and a logic high chooses f2 (frequency tuning word 2, parallel register address aCf hex). changes in frequency are phase-continuous and practically instantaneous. (please refer to pipeline delays in speci?cation table.) other than f2 and pin 29 becoming active, this mode is identical to single-tone. the unramped fsk mode, figure 36, is representative of traditional fsk, rtty (radio teletype) or tty (teletype) transmission of digital data. frequency transitions occur nearly instantaneously from f1 to f2. this simple method works extremely well and is the most reliable form of digital communica- tion, but it is also wasteful of rf spectrum. see the following ramped fsk section for an alternative fsk method that conserves bandwidth. ramped fsk (mode = 010) a method of fsk whereby changes from f1 to f2 are not instantaneous but instead are accomplished in a frequency sweep or ramped fashion. the ramped notation implies that the sweep is linear. while linear sweeping or frequency ramping is easily and automatically accomplished, it is only one of many possibilities. other frequency transition schemes may be implemented by changing the ramp rate and ramp step size on-the-fly, in piecewise fashion. frequency ramping, whether linear or nonlinear, necessitates that many intermediate frequencies between f1 and f2 will be output in addition to the primary f1 and f2 frequencies. fig- ures 37 and 38 graphically depict the frequency versus time characteristics of a linear ramped fsk signal. the purpose of ramped fsk is to provide better bandwidth containment than traditional fsk by replacing the instantaneous frequency changes with more gradual, user-de?ned frequency changes. the dwell time at f1 and f2 can be equal to or much greater than the time spent at each intermediate frequency. the user controls the dwell time at f1 and f2, the number of inter- mediate frequencies and time spent at each frequency. unlike unramped fsk, ramped fsk requires the lowest frequency to be loaded into f1 registers and the highest frequency into f2 registers. several registers must be programmed to instruct the dds regarding the resolution of intermediate frequency steps (48 bits) and the time spent at each step (20 bits). furthermore, the clr acc1 bit in the control register should be toggled (low-high- low) prior to operation to assure that the frequency accumulator is starting from an all zeros output condition. for piecewise, nonlinear frequency transitions, it is necessary to reprogram the registers while the frequency transition is in progress to affect the desired response. f1 f2 0 frequency mode tw1 tw2 fsk data (pin 29) 001 (fsk no ramp) f1 f2 000 (default) 0 0 figure 36. traditional fsk mode f1 f2 0 frequency mode tw1 tw2 fsk data (pin 29) 010 (ramped fsk) f1 f2 000 (default) 0 0 figure 37. ramped fsk mode
ad9852 C19C rev. 0 parallel register addresses 1aC1c hex comprise the 20-bit ramp rate clock registers. this is a count-down counter that outputs a single pulse whenever the count reaches zero. the counter is activated any time a logic level change occurs on fsk input pin 29. this counter is run at the system clock rate, 300 mhz maximum. the time period between each output pulse is given as (n+ 1 ) (system clock period) where n is the 20-bit ramp rate clock value programmed by the user. allowable range of n is from 1 to (2 20 C1). the output of this counter clocks the 48-bit frequency accumulator shown be- low in f igure 39. the ramp rate clock determines the amount of time spent at each intermediate frequency between f1 and f2. the counter stops automatically when the destination frequency is achieved. the dwell time spent at f1 and f2 is determined by the duration that the fsk input, pin 29, is held high or low after the destination frequency has been reached. frequency tuning word 1 20-bit ramp rate clock 48-bit delta- frequency word frequency accumulator phase accumulator out adder fsk (pin 29) system clock frequency tuning word 2 figure 39. block diagram of ramped fsk function parallel register addresses 10C15 hex comprise the 48-bit, straight binary, delta frequency word registers. this 48-bit word is accumulated (added to the accumulators output) every time it receives a clock pulse from the ramp rate counter. the output of this accumulator is then added to or subtracted from the f1 or f2 frequency word, which is then fed to the input of the 48-bit phase accumulator that forms the numerical phase steps for the sine and cosine wave outputs. in this fashion, the output frequency f1 f2 0 frequency mode tw1 tw2 fsk data 010 (ramped fsk) f1 f2 000 (default) 0 0 figure 38. ramped fsk mode is ramped up and down in frequency, according to the logic- state of pin 29. the rate at which this happens is a function of the 20-bit ramp rate clock. once the destination frequency is achieved, the ramp rate clock is stopped, which halts the frequency accumulation process. generally speaking, the delta frequency word will be a much smaller value as compared to that of the f1 or f2 tuning word. for example, if f1 and f2 are 1 khz apart at 13 mhz, the delta frequency word might be only 25 hz. figure 41 shows that premature toggling causes the ramp to immediately reverse itself and proceed at the same rate and resolu- tion back to originating frequency. the control register contains a triangle bit at parallel register address 1f hex. setting this bit high in mode 010 cau ses an automatic ramp-up and ramp-down between f1 and f2 to occur without having to toggle pin 29 as shown in figure 40. in fact, the logic state of pin 29 has no effect once the triangle bit is set high. this function uses the ramp-rate clock time period and the delta-frequency-word step size to form a continuously sweeping linear ramp from f1 to f2 and back to f1 with equal dwell times at every frequency. using this function, one can automatically sweep from dc to the nyquist limit or any other two frequencies between dc and nyquist. f1 f2 0 frequency mode tw1 tw2 fsk data triangle bit 010 (ramped fsk) f1 f2 figure 40. effect of triangle bit in ramped fsk mode
ad9852 C20C rev. 0 in the ramped fsk mode with the triangle bit set high an auto- matic frequency s weep will be gin at either f1 or f2, according to the logic level on pin 29 (fsk input pin) when the triangle bits rising edge occurs as shown in f igure 42. if the fsk data bit had been high instead of low, f2 would have been chosen instead of f1 as the start frequency. f2 f1 0 frequency mode tw1 tw2 fsk data triangle bit 000 (default) 0 0 010 (ramped fsk) f1 f2 figure 42. a utomatic linear ramping using the triangle bit additional flexibility in the ramped fsk mode is provided in the ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp-rate counter on-the-fly during the ramping from f1 to f2 or vice versa. to create these nonlinear frequency changes it is necessary to combine several linear ramps in a piecewise fashion whose slopes are different. this is done by programming and executing a linear ramp at some rate or slope and then altering the slope (by changing the ramp rate clock or delta frequency word or both). changes in slope are made as often as needed to form the desired nonlinear frequency sweep response before the destination frequency has been reached. these piecewise changes can be precisely timed using the 32-bit internal update clock (see detailed description elsewhere in this data sheet). f1 f2 0 frequency mode tw1 tw2 fsk data f1 f2 000 (default) 0 0 010 (ramped fsk) figure 41. effect of premature ramped fsk data nonlinear ramped fsk will have the appearance of a chirp function that is graphically illustrated in figure 43. the major difference between a ramped fsk function and a chirp function is that fsk is limited to operation between f1 and f2. chirp operation has no f2 limit frequency. two additional control bits are available in the ramped fsk mode that allow even more options. clr acc1, register address 1f hex, will, if set high, clear the 48-bit frequency accumulator (acc1) output with a retriggerable one-shot pulse of one system clock duration. if the clr acc1 bit is left high, a one-shot pulse will be delivered on the rising edge of every update clock. the effect is to interrupt the current ramp, reset the frequency back to the start point, f1 or f2, and then continue to ramp up (or down) at the previous rate. this will occur even when a static f1 or f2 destination frequency has been achieved. (see figure 43.) next, clr acc2 control bit (register address 1f hex) is avail- able to clear both the frequency accumulator (acc1) and the phase accumulator (acc2). when this bit is set high, the output of the phase accumulator will result in 0 hz output from the dds. as long as this bit is set high, the frequency and phase accumula- tors will be cleared, resulting in 0 hz output. to return to previous dds operation, clr acc2 must be set to logic low. chirp (mode 011) this mode is also known as pulsed fm. most chirp systems use a linear fm sweep pattern although any pattern may be used. this is a type of spread spectrum modulation that can realize pro cessing gain. in radar applications, use of chirp or pulsed fm allows operators to signi?cantly reduce the output power needed to achieve the same result as a single-frequency radar system would produce. figure 43 represents a very low-resolution nonlinear chirp meant to demonstrate the different slopes that are created by varying the time steps (ramp rate) and frequency steps (delta frequency word). the ad9852 permits precise, internally generated linear or externally programmed nonlinear pulsed or continuous fm over a user-de?ned frequency range, duration, frequency resolution and sweep direction(s). a block diagram of the fm chirp components is shown in figure 44.
ad9852 C21C rev. 0 20-bit ramp rate clock 48-bit delta- frequency word frequency accumulator phase accumulator out adder system clock clr acc2 clr acc1 frequency tuning word 1 hold figure 44. fm chirp components basic fm chirp programming steps 1. program a start frequency into frequency tuning word 1 (parallel register addresses 4C9 hex) hereafter called ftw1. 2. program the frequency step resolution into the 48-bit, twos complement, delta frequency word (parallel register addresses 10C15 hex). 3. program the rate of change (time at each frequency) into the 20-bit ramp rate clock (parallel register addresses 1aCc). 4. when programming is complete, an i/o update pulse at pin 20 will engage the program commands. the necessity for a twos complement delta frequency word is to de?ne the direction in which the fm chirp will move. if the 48-bit delta frequency word is negative (msb is high), the incremental frequency changes will be in a negative direction from ftw1. if the 48-bit word is positive (msb is low), the incre- mental frequency changes will be in a positive direction. f1 0 frequency 010 (ramped fsk) f1 000 (default) 0 mode tw1 dfw ramp rate figure 43. example of a nonlinear chirp it is important to note that the ftw1 is only a starting point for fm chirp. there is no built-in restraint requiring a return to ftw1. once the fm chirp has left ftw1 it is free to move (under program control) within the nyquist bandwidth (dc to 1/2 system clock). instant return to ftw1 is easily achieved, though, and this option is explained in the next few paragraphs. two control bits are available in the fm chirp mode that will allow practically instantaneous return to the beginning frequency, ftw1, or to 0 hz. first, clr acc1 bit, register address 1f hex will, if set high, clear the 48-bit frequency accumulator (acc1) output with a retriggerable one-shot pulse of one system clock duration. the 48-bit delta frequency word input to the accu- mulator is unaffected by clr acc1 bit. if the clr acc1 bit is left high, a one-shot pulse will be delivered to the frequency accumulator (acc1) on every rising edge of the i/o update clock. the effect is to interrupt the current chirp, reset the frequency back to ftw1, and continue the chirp at the previously programmed rate and direction. clearing the frequency accum ulator in the chirp mode is illustrated in figure 45. not shown in the diagram is the i/o update signal, which is either user-supplied or internally generated. a discussion of i/o up date is presented elsewhere in this data sheet. next, clr acc2 control bit (register address 1f hex) is available to clear both the frequency accumulator (acc1) and the phase accum ulator (acc2). when this bit is set high, the output of the phase accumulator will result in 0 hz output from the dds. as long as this bit is set high, the frequency and phase accumulators will be cleared, resulting in 0 hz output. to return to previous dds operation, clr acc2 must be set to logic low. this bit is useful in generating pulsed fm.
ad9852 C22C rev. 0 fm chirp figure 46 graphically illustrates the effect of clr acc2 bit upon the dds output frequency. note that reprogramming the registers while the clr acc2 bit is high allows a new ftw1 frequency and slope to be loaded. another function available only in the chirp mode is the hold pin, pin 29. this function will stop the clocking signal to the ramp rate counter that will, in turn, halt any further clocking pulses to the frequency accumulator, acc1. the effect is to halt the chirp and hold the output frequency in a static condition at the frequency existing just before hold was pulled high. when the hold pin is returned low, the clocks are resumed and chirp continues. during a hold condition, user may change the programming registers; however, the ramp rate counter must resume operation at its previous rate until a count of zero is obtained before a new ramp rate count can be loaded. figure 47 illustrates the effect of the hold function on the dds output frequency. users may utilize the 32-bit automatic i/o update counter when constructing complex chirp or ramped fsk se quences. since this internal counter is synchronized with the ad9852 s ystem update clock f1 0 frequency mode ftw1 dfw f1 000 (default) 0 ramp rate ramp rate 011 (chirp) delta frequency word clr acc1 figure 45. effect of clr acc1 in fm chirp mode clr acc2 f1 0 frequency mode tw1 dpw 000 (default) 0 ramp rate 011 (chirp) figure 46. effect of clr acc2 in fm chirp mode clock, it allows precisely timed program changes to be invoked. in this manner, user is only required to reprogram the desired registers before the automatic i/o update pulse is generated. a complete discussion of this function is presented elsewhere in this data sheet. in the chirp mode, the destination frequency is not directly speci?ed. if the user fails to control the chirp, the dds will control itself by naturally con?ning its output between dc and nyquist; however, unless terminated by the user, the chirp will continue until power is removed. it is the users choice as to what occurs when the chirp destination frequency is reached. here are a few of the choices: 1. stop and hold at the destination frequency using the hold pin, or by loading all zeros into the delta frequency word registers of the frequency accumulator (acc1). 2. stop using the hold pin function, then ramp-down the out- put amplitude using the digital multiplier stages and the shaped keying pin, pin 30, or via program register control (addresses 21C24 hex). 3. stop and abruptly terminate the transmission using the clr acc2 bit.
ad9852 C23C rev. 0 4. continue chirp by reversing direction and returning to the previous, or another, destination frequency in a linear or user- directed manner. if this involves going down in frequency, a negative 48-bit delta frequency word (the msb is set to 1) must be loaded into registers 10C15 hex. any decreasing fre- quency step of the delta frequency word requires the msb to be set to logic high. 5. continue chirp by immediately returning to the f1 beginning frequency in a sawtooth fashion and repeat the previous chirp process again. this is where clr acc1 control bit is used. an automatic, repeating chirp can be setup using the 32-bit update clock to issue clr acc1 commands at precise time intervals. adjusting the timing intervals or changing the delta frequency word will change the chirp range. it is incum bent upon the user to balance the chirp duration and frequency resolution to achieve the proper frequency range. bpsk (mode 100) binary, biphase, or bipolar phase shift keying is a means to rapidly select between two preprogramming 14-bit output phase offsets that will identically affect both the i and q outputs of the ad9852. the logic-state of pin 29, bpsk pin, controls the selection of phase adjust register number 1 or 2. when low, pin 29 selects hold f1 0 frequency mode tw1 dfw 000 (default) 0 ramp rate 011 (chirp) f1 delta frequency word ramp rate figure 47. illustration of hold function phase adjust register 1; when high, phase adjust register 2 is selected. figure 48 illustrates phase changes made to four cycles of an output carrier. basic bpsk programming steps: 1. program a carrier frequency into frequency tuning word 1. 2. program appropr iate 14-bit phase words in phase adjust registers 1 and 2. 3. attach bpsk data source to pin 29. 4. activate i/o update pulse when ready. if phase shift keying is not the objective, but rather a broader range of phase offsets is needed, the user should select the single- tone mode and program phase adjust register 1 using the serial or high-speed parallel programming bus. i/o port buffers 100 mhz, 8-bit parallel or 10 mhz serial loading, spi-compatible. the programming mode is selected externally via the serial/parallel (s/p select) pin. i/o buffers can be written to, or read from, according to the signals supplied to the read (rdb) and write pins (wrb) and the 6-bit address (a0Ca5) in the parallel mode or to csb, sclk and sdio pins in the serial mode. bpsk data 360 0 phase mode ftw1 phase adjust 1 000 (default) 0 phase adjust 2 100 (bpsk) f1 270 degrees 90 degrees phase after onset phase before onset figure 48. bpsk mode
ad9852 C24C rev. 0 data in the i/o port buffers is stored until overwritten by changes in program instructions supplied by the user or until power is removed. an i/o update clocks-in the data from the i/o buffers to the dds programming registers where it is executed. am amplitude modulation of the sine dacs is possible u sing the i/o port to control 12-bit digital multiplier stages that precede the dacs. the multipliers can also be used to set the dac outputs between zero- and full-scale for static amplitude adjust- ment. see the shaped on/off keying description for more information. shaped keying function does not apply to the control dac. high-speed comparator optim ized for high sp eed, >300 mhz toggle rate, low jitter, sensitive input, built-in hysteresis and an output level of 1 v p-p minimum into 50 w or cmos logic levels into high impedance loads. the comparator can be sepa- rately powered down to conserve power. this com parator is used in clock generator applications to square up a bandpass or low-pass ?ltered sine wave. eight-bit ramp rate clock when shaped on/off keying is engaged, this down-counter takes the system clock (300 mhz maximum), and divides it by an 8-bit binary value (programmed by the user) to produce a user-de?ned clock. the clock outputs one pulse every time the counter counts down to zero. this clock is used to set the rate-of-change of the 12-bit digital multipliers of the i and q dacs to perform an output shaping function. twenty-bit ramp rate clock when selected, this down- counter takes the system clock (300 mhz maximum) and divides it by a 20-bit binary value (programmed by the user) to produce a user-de?ned clock. the clock outputs one pulse every time the counter counts down to zero. this clock is used to set the rate-of-frequency-change of the ramped fsk or fm chirp modes. forty-eight-bit delta frequency register is used only in the chirp and ramped-fsk modes. this register is loaded with a 48-bit word that represents the frequency increment value of frequency accumulator (accu 1) whose output will be added to a frequency that is set in either f1 or f2 frequency registers. this register is periodically incremented at a rate set by the 20-bit ramp rate clock (150 mhz maximum). forty-eight-bit delta frequency register is programmed with a 48-bit frequency tuning word that is input to the 48-bit phase accumulator (accu 2) and determines the output fre- quency of the dds in the single-tone mode. when ramped-fsk or chirp are selected, this register is sent to a digital adder where it is summed with the output of accu 1 before being input to accu 2. therefore, the signal sent to accu 2 may be either static or changing at a rate of up to 150 million 48-bit frequency tuning words per second. power-down several individual stages, when not needed, can be powered down to reduce power consumption via the programming registers while still maintaining functionality of desired stages. these stages are identi?ed in the register layout table, address 1d hex. power-down is achieved by setting the speci?ed bits to logic high. a logic low indicates that the stages are powered up. furthermore, and perhaps most signi?cantly, two intensely digital stages, the inverse sinc ?lters and the digital multiplier stages, can be bypassed to achieve signi?cant power reduction through programming of the control registers in address 20 hex. again, logic high will cause the stage to be bypassed. of particular importance is the inverse sinc ?lter as this stage consumes a signi?cant amount of power. a full power-down occurs when all four pd bits in control register 1d hex are set to logic high. this reduces power consumption to approximately 10 mw (3 ma). master reset logic high active, must be held high for a minimum of 10 system clock cycles. this causes the communi- cations bus to be initialized and loads default values listed in the table v.
ad9852 C25C rev. 0 table v. register layout. shaded sections comprise the control register parallel serial address address ad9852 register layout default hex hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value 00 0 phase adjust register #1 <13:8> (bits 15, 14 dont care) phase 1 00h 01 phase adjust register #1 <7:0> 00h 02 1 phase adjust register #2 <13:8:> (bits 15, 14 dont care) phase 2 00h 03 phase adjust register #2 <7:0> 00h 04 2 frequency tuning word 1 <47:0> frequency 1 00h 05 frequency tuning word 1 <39:32> 00h 06 frequency tuning word 1 <31:24> 00h 07 frequency tuning word 1 <23:16> 00h 08 frequency tuning word 1 <15:8> 00h 09 frequency tuning word 1 <7:0> 00h 0a 3 frequency tuning word 2 <47:40> frequency 2 00h 0b frequency tuning word 2 <39:32> 00h 0c frequency tuning word 2 <31:24> 00h 0d frequency tuning word 2 <23:16> 00h 0e frequency tuning word 2 <15:8> 00h 0f frequency tuning word 2 <7:0> 00h 10 4 delta frequency word <47:40> 00h 11 delta frequency word <39:32> 00h 12 delta frequency word <31:24> 00h 13 delta frequency word <23:16> 00h 14 delta frequency word <15:8> 00h 15 delta frequency word <7:0> 00h 16 5 update clock <31:24> 00h 17 update clock <23:16> 00h 18 update clock <15:8> 00h 19 update clock <7:0> 40h 1a 6 ramp rate clock <19:16> (bits 23, 22, 21, 20 dont care) 00h 1b ramp rate clock <15:8> 00h 1c ramp rate clock <7:0> 00h 1d 7 dont dont dont comp pd reserved, control dac pd dig pd 00h care care care always dac pd 1e low 1f dont pll bypass ref mult 4 ref mult 3 ref mult 2 ref mult 1 ref mult 0 64h care range pll 20 clr clr triangle dont care mode 2 mode 1 mode 0 int update 01h acc 1 acc 2 clk dont bypass osk en osk int dont dont lsb first sdo 20h care inv care care active sinc 21 8 output shape key i mult <11:8> (bits 15, 14, 13, 12 dont care) 00h 22 output shape key i mult <7:0> 00h 23 9 output shape key q mult <11:8> (bits 15, 14, 13, 12 dont care) 00h 24 output shape key q mult <7:0> 00h 25 a output shape key ramp rate <7:0> 80h 26 b qdac <11:8> (bits 15, 14, 13, 12 dont care) 00h 27 qdac <7:0> (data is required to be in twos-complement format) 00h
ad9852 C26C rev. 0 interfacing and programming the ad9852 the ad9852 register layout, shown in table v, contains the information that programs the chip for the desired functionality. while many applications will require very little programming to con?gure the ad9852, some will make use of all twelve acces- sible register banks. the ad9852 supports an 8-bit byte parallel i/o operation or an spi-compatible serial i/o operation. all accessible registers can be written and read back in either i/o operating mode. an external pin, s/p select, is used to con?gure the i/o mode. systems that use the parallel i/o mode must connect the s/p select pin to v dd . systems that operate in the serial i/o mode must tie the s/p select pin to gnd. regardless of mode, the i/o port data is written to a buffer memory that does not affect operation of the part until the contents of the buffer memory are transferred to the register banks. this transfer of information occurs, synchronously, to the system clock and occurs in one of two ways: a<5:0> d<7:0> rd a1 d1 a2 d2 a3 d3 t rdhoz t rdlov t ahd t adv specification value description t adv t ahd t rdlov t rdhoz 15 5 15 10 address to data valid time (maximum) address hold time to rd signal inactive (minimum) rd low to output valid (maximum) rd high to data three-state (maximum) figure 49. parallel port read timing diagram d<7:0> wr d1 d2 d3 specification value description t asu t dsu t adh t dhd 4ns 2ns address setup time to wr signal active data setup time to wr signal inactive 5ns 0ns address hold time to wr signal inactive data hold time to wr signal inactive t wrlow t wrhigh t wr 3ns wr signal minimum low time 7ns 3ns wr signal minimum high time wr signal minimum period a<5:0> a1 a2 a3 t asu t ahd t wrhigh t wrlow t dhd t dsu t wr figure 50. parallel port write timing diagram 1. internally, controlled at a rate programmable by the user or, 2. externally, controlled by the user. i/o operations can occur in the absence of refclk but the data cannot be moved from the buffer memory to the register bank without refclk. see the update clock operation section of this document for details. parallel i/o operation with the s/p select pin tied high, the parallel i/o mode is active. the i/o port is compatible with industry standard dsps and microcontrollers. six address bits, eight bidirectional data bits and separate write/read control inputs make up the i/o port pins. parallel i/o operation allows write access to each byte of any register in a single i/o operation at 100 mhz. readback capability for each register is included to ease designing with the ad9852. reads are not guaranteed at 100 mhz as they are intended for software debug only. parallel i/o operation timing diagrams are shown in the figures 49 and 50.
ad9852 C27C rev. 0 serial port i/o operation with the s/p select pin tied low, the serial i/o mode is active. the ad9852 serial port is a flexible, sync hronous, serial communications port allowing easy interface to many industry -standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. the interface allows read/write access to all twelve registers that con?gure the ad9852 and can be con?gured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/ sdo). data transfers are supported in most signi?cant bit (msb) ?rst format or least signi?cant bit (lsb) ?rst for mat at up to 10 mhz. when con?gured for serial i/o operation, most pins from the ad9852 parallel port are inactive; some are used for the serial i/o. table vi describes pin requirements for serial i/o. table vi. serial i/o pin requirements pin pin number name serial i/o description 1, 2, 3, 4, d[7:0] the parallel data pins are not active, tie 5, 6, 7, 8 to vdd or gnd. 14, 15, 16 a[5:3] the parallel address pins a5, a4, a3 are not active, tie to vdd or gnd. 17 a2 ioreset 18 a1 sdo 19 a0 sdio 20 i/o ud update clock. same functionality for serial mode as parallel mode. 21 wrb sclk 22 rdb csbchip select general operation of the serial interface there are two phases to a communication cycle with the ad9852. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9852, coincident with the ?rst eight sclk rising edges. the instruction byte provides the ad9852 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte de?nes whether the upcoming data transfer is read or write, and the register address in which to transfer data to/from. the ?rst eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9852. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9852 and the system controller. the number of data bytes transferred in phase 2 of the communication cycle is a function of the regis- ter address. the ad9852 internal serial i/o controller expects every byte of the register being accessed to be transferred. table vii describes how many bytes must be transferred. table vii. register address vs. data bytes transferred serial number register of bytes address register name transferred 0 phase offset tuning word register #1 2 bytes 1 phase offset tuning word register #2 2 bytes 2 frequency tuning word #1 6 bytes 3 frequency tuning word #2 6 bytes 4 delta frequency register 6 bytes 5 update clock rate register 4 bytes 6 ramp rate clock register 3 bytes 7 control register 4 bytes 8 i path digital multiplier register 2 bytes 9 q path digital multiplier register 2 bytes a shaped on/off keying ramp rate register 2 bytes b q dac register 2 bytes at the completion of any communication cycle, the ad 9852 serial port controller expects the next eight rising sclk edges to be the instruction byte of the next communication cycle. in addition, an active high input on the ioreset pin immediately terminates the current communication cycle. after ioreset returns low, the ad9852 serial port controller requires the next eight rising sclk edges to be the instruction byte of the next communication cycle. all data input to the ad9852 is registered on the rising edge of sclk. all data is driven out of the ad9852 on the falling edge of sclk. figures 51 and 52 are useful in understanding the general opera- tion of the ad9852 serial port. instruction cycle data transfer instruction byte data byte 1 data byte 2 data byte 3 sdio cs figure 51. using sdio as a read/ write transfer instruction cycle data transfer instruction byte sdio cs data transfer data byte 1 data byte 2 data byte 3 sdo figure 52. using sdio as an input, sdo as an output
ad9852 C28C rev. 0 instruction byte the instruction byte contains the following information. table viii. instruction byte information msbd6 d5d4 d3 d2d1lsb r/ w xxxa3a2a1a0 r/ w bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. logic high indicates read operation. logic zero indicates a write operation. bits 6, 5, and 4 of the instruction byte are dont care. a3, a2, a1, a0bits 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. see table viii for register address details. serial interface port pin description sclk serial clock (pin 21). the serial clock pin is used to synchronize data to and from the ad9852 and to run the internal state machines. s clk maximum frequency is 10 mhz. cs chip select (pin 22). active low input that allows more than one device on the same serial communications lines. the sdo and sdio pins will go to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until cs is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdio serial data i/o (pin 19). data is always written into the ad9852 on this pin. however, this pin can be used as a bidirectional data line. the con?guration of this pin is controlled by bit 0 of register address 20h. the default is logic zero, which con?gures the sdio pin as bidirectional. sdo serial data out (pin 18). data is read from this pin for proto- cols that use separate lines for transmitting and receiving data. in the case where the ad9852 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. io reset synchronize i/o port (pin 17). synchronizes the i/o port state machines without affecting the addressable registers contents. an active high input on io reset pin causes the current commu- nication cycle to terminate. after io reset returns low (logic 0) another communication cycle may begin, starting with the instruction byte write. notes on serial port operation the ad9852 serial port con?guration bits reside in bits 1 and 0 of register address 20h. it is important to note that the con- ?guration changes immediately upon a valid i/o update. for multibyte transfers, writing this register may occur dur ing the middle of a commu nication cycle. care must be taken to com- pensate for this new con?guration for the remainder of the current communication cycle. the system must maintain synchronization with the ad9852 or the internal control logic will not be able to recognize further instructions. for example, if the system sends the instruction to write a 2-byte register, then pulses the sclk pin for a 3-byte register (24 additional sclk rising edges), communication synchronization is lost. in this case, the ?rst 16 sclk rising edges after the instruction cycle will properly write the ?rst two data bytes into the ad9852, but the next eight rising sclk edges are interpreted as the next instruction byte, not the ?nal byte of the previous communication cycle. in the case where synchronization is lost between the system and the ad9852, the io reset pin provides a means to reestablish synchronization without reinitializing the entire chip. asserting the io reset pin (active high) resets the ad9852 serial port state machine, terminating the current io operation and putting the device into a state in which the next eight sclk rising edges are understood to be an instruction byte. the sync io pin must be deasserted (low) before the next instruction byte write can begin. any information that had been written to the ad9852 registers during a valid communication cycle prior to loss of synchronization will remain intact. cs sclk sdio t pre t dsu t sclkpwh t sclkpwl t sclk t dhld 2nd bit 1st bit symbol min definition cs setup time period of serial data clock serial data setup time serial data clock pulsewidth high serial data clock pulsewidth low serial data hold time t pre t sclk t dsu t sclkpwh 30ns 100ns 30ns 40ns t sclkpwl t dhld 40ns 0ns figure 53. timing diagram for data write to ad9852 t dv 1st bit 2nd bit sdio sdo sclk cs symbol max definition t dv 30ns data valid time figure 54. timing diagram for read from ad9852
ad9852 C29C rev. 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 17 16 15 14 13 12 11 10 sdio sclk cs ir write phase data transfer C two-byte write figure 55. data write cycle, sclk idle high b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 17 16 15 14 13 12 11 10 sdio sdo sclk cs ir write phase data transfer C two-byte read figure 56. data read cycle, 3-wire con?guration, sclk idle low msb/lsb transfers the ad9852 serial port can support both most signi?cant bit (msb) ?rst or least signi?cant bit (lsb) ?rst data formats. this functionality is controlled by bit 1 of serial register bank 20h. when this bit is set active high, the ad9852 serial port is in lsb ?rst format. this bit defaults low, to the msb ?rst format. the in struction byte must be written in the format indicated by bit 1 of serial register bank 20h. that is, if the ad9852 is in lsb ?rst mode, the instruction byte must be written from least signi?cant bit to most signi?cant bit. update clock operation programming the ad9852 is asynchronous to the system clock with all data being stored in a buffer memory that does not immediately affect the part operation. the buffer memory is transferred to the register bank synchronous to system clock. the register bank information affects part operation. this transfer of data can occur automatically, with frequency of updates programmable by the user, or can occur completely under user control. complete user control, referred to as external update mode, allows the user to drive the i/o ud signal from their asic or dsp. the ad9852 i/o ud pin is con?gured as an input in external update mode. a rising edge on i/o ud indicates to the ad9 852 that the contents of the buffer memory is to be transferred to the register bank. the design uses an edge detector to signal the ad9852 to transfer data which allows a very small minimum high pulse width requirement (two system clock peri- ods). its important to note that if the user keeps i/o ud high, the ad9852 will not continuously update the register bank. internal update mode, in which the ad9852 transfers data from the buffer memory to the register bank automatically, con?gures the ad9852 i/o ud pin as an output. the ad9852 generates a high pulse on i/o ud pin to signal the user that the buffer memory has just been transferred to the register bank. the minimum high pulsewidth is designed to be eight system clock cycles (min). the i/o ud signal can be used as an interrupt within the system. its important to note that as an output i/o ud pin will not have anything approaching a 50/50 duty cycle for slower update rates. programming the update clock register for values less than ?ve will cause the i/o ud pin to remain high. the update clock func- tionality still works, its just that the user cannot use the signal as an indication that data is transferring. this is an affect of the minimum high pulse time when i/o ud is an output. for internal update clock operation, the rate which the updates occur is programmed into the update clock register. the update clock register is 32 bits and the value written into the register corresponds to half the number of clock cycles between updates. that is, if a value of 00_00_00_0a (hex), is written into the update clock register the rising edge of the i/o ud pin will occur every 20 cycles (0a hex equals 10 decimal). control register the control register is located in the shaded portion of the table v at address 1d through 20 hex. it is composed of 32 bits. bit 31 is located at the top left position and bit 0 is located in the lower right position of the shaded table portion. the reg- ister has been subdivided below to make it easier to locate the text associated with speci?c control categories.
ad9852 C30C rev. 0 power-down functions four bits are available to power down the ad9852. each bit is active high, that is, they default low and a logic 1 causes the power-down function to be working, the four bits all reside in the same control byte such that one io write cycle can complete a full power-down by writing all four bits true simultaneously. the four bits are located in control register [28, 26:24] and are described below. the default state for these bits is logic 0, inactive. cr[31:29] are open. cr[28] is the comparator power-down bit. when set (logic 1), this signal indicates to the comparator that a power-down mode is active. cr[27] must always be written to logic zero. writing this bit to logic 1 causes the ad9852 to stop working until a master reset is applied. cr[26] is the control dac power-down b it. when set (logic 1), this signal indicates to the control dac that a power- down mode is active. cr[25] is the full dac power-down bit. when set (logic 1), this signal indicates to both the cosine and control dacs, as well as the reference, that a power-down mode is active. cr[24] is the digital power-down bit. when set (logic 1), this signal indicates to the digital section that a power-down mode is active. within the digital section, the clocks will be forced to dc, effectively powering down the digital section. the refclk input will still be seen by the pll and the pll will continue to output the higher frequency. refclk multiplier pll functions seven control register bits, located in the control register [22:16] positions, re late to the pll. cr[23] is reserved, write to zero. cr[22] is the pll range bit. the pll range bit controls the vco gain. the power-up state of the pll range bit is logic 1, higher gain for frequencies above 200 mhz. cr[21] is the bypass pll bit, active high. when active, the pll is powered down and the refclk input is used to drive the system clock signal. the power-up state of the bypass pll bit is logic 1, pll bypassed. cr[20:16] bits are the pll multiplier factor. these bits are the refclk multiplication factor unless the bypass pll bit is set. the pll multiplier valid range is from 4 to 20, inclusive. other operational functions cr[15] is the clear accumulator 1 bit. this bit has a one-shot type function. when written active, logic 1, a clear accumulator 1 signal is sent to the dds logic, resetting the accumulator value to zero. the bit is then automatically reset, but the buffer memory is not reset. this bit allows the user to easily create a sawtooth frequency sweep pattern with very little (or no) user input required. t his bit is intended for chirp mode only, but there is no logic to suppress its functionality in other modes. cr[14] is the clear accumulator bit. this bit, active high, holds both the accumulator 1 and accumulator 2 values at zero for as long as the bit is active. this allows the dds phase to be initial- ized via the i/o port. cr[13] is the triangle bit. when this bit is set, the ad9852 will automatically perform a continuous frequency sweep from the frequency 1 to frequency 2 and back. the effect is a triangular frequency sweep. when this bit is set, the operating mode must be set to ramped fsk. cr[11:9] are the three bits that describe the ?ve operating modes of the ad9852: 0h = single-tone mode 1h = fsk mode 2h = ramped fsk mode 3h = chirp mode 4h = psk mode cr[8] is the internal update active bit. when this bit is set to logic 1, the i/o ud pin is an output and the ad9852 generates the i/o ud signal. when logic 0, external i/o ud functionality is performed, the i/o ud pin is con?gured as an input. cr[7] reserved, write to zero. cr[6] is the bypass of the inverse sinc ?lter bit. when set, the data from the dds block goes directly to the shaped keying logic and the clock to the inverse sinc ?lter is stopped. d efault is clear, ?l ter enabled. cr[5] is the shaped keying enable bit. when set the output ramping function is enabled and is performed in accordance with the cr[4] bit requirements. cr[4] is the internal/external shaped keying control bit. when set logic 1, the shaped keying factor will be internally gen erated and applied to the i path. when clear, the shaped keying f unction is externally controlled by the user and the shaped keying factor is the i output shaped keying register values. the two registers that are the ramp factors also default low such that the output is off at power-up and until the device is programmed by the user. cr[3:2] reserved, write to zero. cr[1] is the serial port msb/lsb ?rst bit. defaults low, msb ?rst. cr[0] is the serial port sdo active bit. defaults low, inactive.
ad9852 C31C rev. 0 power dissipation and thermal considerations the ad9852 is a multifunctional, very high-speed device that targets a wide variety of synthesizer and agile clock applications. the set of numerous innovative features contained in the device each consume incremental power, the sum of which, if enabled in combination, may exceed the safe thermal operating condi- tions of the device. careful analysis and consideration of power dissipation and thermal management is a critical element in the successful application of the ad9852 device. the ad9852 device is speci?ed to operate within the industrial temperature range of C40 c to +85 c. this speci?cation is conditional, how ever, such that the absolute maximum junction temperature of 150 c is not exceeded. at high operating tempera- tures, extreme care must be taken in the operation of the device to avoid exceeding the junction temperature which results in a potentially damaging thermal condition. many variables contribute to the operating junction temperature within the device, including: 1. package style 2. selected mode of operation 3. internal system clock speed 4. supply voltage 5. ambient temperature. the combination of these variables determines the junction temperature within the ad9852 device for a given set of operating conditions. the ad9852 device is available in two package styles: a thermally- enhanced surface-mount package with an exposed heat sink, and a nonthermally-enhanced surface-mount package. the thermal impedance of these packages are 16 c/w and 38 c/w respectively, measured under still air conditions. thermal impedance the thermal impedance of a package can be thought of as a thermal resistor that exists between the semiconductor surface and the ambient air. the thermal impedance of a package is determined by package material and its physical dimensions. the dissipation of the heat from the package is directly dependent upon the ambient air conditions and the physical connection made between the ic package and the pcb. adequate dissipation of power from the ad9852 relies upon all power and ground pins of the device being soldered directly to a copper plane on a pcb. in addition, the thermally-enhanced package of the ad9852asq contains a heat sink on the bottom of the package that must be soldered to a ground pad on the pcb surface. this pad must be connected to a large copper plane which, for convenience, may be ground plane. sockets for either package style of the ad9852 device are not recommended. junction temperature considerations the power dissipation (p diss ) of the ad9852 device in a given application is determined by many operating conditions. some of the conditions have a direct relationship with p diss , such as supply voltage and clock speed, but others are less deterministic. the total power dissipation within the device, and its effect on the j unction temperature, must be considered when using the device. the ju nction temperature of the device is given by: j unction temperature = (thermal impedance power consumption) + ambient temperature given that the junction temperature should never exceed 150 c for the ad9852, and that the ambient temperature can be 85 c, the maximum power consumption for the ad9852ast is 1.7 w and the ad9852asq (thermally-enhanced package) is 4.1 w. factors affecting the power dissipation are: supply voltage this obviously affects power dissipation and junction temperature since p diss equals v i. users should design for 3.3 v nominal, however the device is guaranteed to meet speci?cations over the full temperature range and over the supply voltage range of 3.135 v to 3.465 v. clock speed this directly and linearly influences the total power dissipation of the d evice and, therefore, junction tem perature. as a rule, to minimize power dissipation, the user should always select the lowest internal clock speed possible to support a g iven application. normally the usable frequency output bandw idth from a dds is limited to 40% of the clock rate to keep r easonable requirements on the output low-pass ?lter. for the typical dds application, the system clock frequency should be 2.5 times the highest desired output frequency. mode of operation the selected mode of operation for the ad9852 has a great influence on total power consumption. the ad9852 offers many features and modes, each of which imposes an additional power requirement. the collection of features contained in the ad9852 target a wide variety of applications and the device was designed under the assumption that only a few would be enabled for any given application. in fact, the user must understand that enabling multiple features at higher clock speeds may cause the junction temperature of the die to be exceeded. this can severely limit the long-term reliability of the device. figure 57 provides a summary of the power require- ments associated with the individual features of the ad9852. this table should be used as a guide in determining the optimum application of the ad9852 for reliable operation. as can be seen in the figure 57, the inverse sinc ?lter function requires a signi?cant amount of power, and much for ethought and scrutiny should be given to its use. as an alternate approach to maintaining flatness across the output bandwidth, the digital multiplier function may be used to adjust the output signal level, at a dramatic savings in power consumption. careful plan- ning and management in the use of the feature set will minimize power dissipation and avoid exceeding junction temperature requirements within the ic.
ad9852 C32C rev. 0 frequency C mhz 1400 20 supply current C ma 1200 1000 800 600 400 200 0 60 100 140 180 220 260 300 figure 57a. power consumption vs. clock frequency showing supply current consumption when all optional circuitry is enabled frequency C mhz 450 20 supply current C ma 400 350 300 250 200 150 0 60 100 140 180 220 260 300 100 50 multipliers inverse sinc aux dac comparator figure 57b. decrease in current consumption when vari- ous circuitry is disabled evaluation of operating conditions the ?rst step in applying the ad9852 is to select the internal clock frequency. clock frequency selections above 200 mhz will require the thermally-enhanced package (ad9852asq); clock frequency selections of 200 mhz and below may allow the user to use the standard plastic surface-mount package, but more information will be needed to make that determination. the second step is to determine the maximum required operating temperature for the ad9852 in the given application. subtract this value from 150 c, which is the maximum junction tem- perature a llowed for the ad9852. for the extended industrial temperature range of 85 c, the result will be 65 c. this is the maximum rise in temperature that the junction may experience due to power dissipation. the third step is to divide this maximum rise number by the thermal impedance, to arrive at the maximum power dissipation allowed for the application. for the example, so far, 65 c divided by both versions of the ad9852 packages thermal impedances of 38 c/w and 16 c/w, yields a total power dissipation limit of 1.7 w and 4.1 w (respectively). this means that for a 3.3 v nominal power supply voltage, the current consumed by the device under full operating conditions must not exceed 515 ma in the standard plastic package and 1242 ma in the thermally-enhanced package. the total set of enabled functions and operating condi- tions of the ad9852 application must support these current consumption limits. figure 57a and 57b may be used to determine the suitability of a given ad9852 application vs. power dissipation requirements. these graphs assume that the ad9852 device will be soldered to a multilayer pcb per the recommended best manufacturing practices and procedures for the given package type. this en sures that the speci?ed thermal impedance speci?cations will be achieved. thermally enhanced package mounting guidelines the following are general recommendations for mounting the thermally enhanced exposed heat sink package (ad9852asq) to printed circuit boards. the exceptional thermal characteristics of this package depend entirely upon proper mechanical attachment. figure 58 depicts the package from the bottom and shows the dimensions of the exposed heat sink. a solid conduit of solder needs to be established between this pad and the surface of the pcb. figure 59 depicts a general pcb land pattern for such an exposed heat sink device. note that this pattern is for a 64-lead device not an 80-lead, but the relative shapes and dimensions still apply. in this land pattern, a solid copper plane exists inside of the individual lands for device leads. note also that the solder mask opening is conservatively dimensioned to avoid any assembly problems. c o u n t r y 14mm 10mm figure 58.
ad9852 C33C rev. 0 solder mask opening thermal land figure 59. the thermal land itself must be able to distribute heat to an even larger copper plane such as an internal ground plane. vias must be uniformly provided over the entire thermal pad to connect to this internal plane. a proposed via pattern is shown in figure 60. via holes should be small (12 mils, 0.3 mm) such that they can be plated and plugged. these will provide the mechanical conduit for heat transfer. figure 60. finally, a proposed stencil design is depicted for screen solder placement. note that if vias are not plugged, wicking will occur which will displace solder away from the exposed heat sink and the necessary mechanical bond will not be established. figure 61. evaluation board an evaluation board is available that supports the ad9852 dds devices. this evaluation board consists of a pcb, software, and documentation to facilitate bench analysis of the performance of the ad9852 device. it is recommended that users of the ad9852 familiarize themselves with the operation and performance capabilities of the device with the evaluation board. the evaluation board should also be used as a pcb reference design to ensure optimum dynamic performance from the device. operating instructions to assist in proper placement of the pin-header shorting-jumpers, the instructions will refer to direction (left, right, top, bottom) as well as header pins to be shorted. pin #1 for each three pin- header has been marked on the pcb corresponding with the schematic diagram. when following these instructions, position the pcb so that the text can be read from left to right. the board is shipped with the pin-headers con?guring the board as follows: 1. refclk for the ad9852 is con?gured as differential. the differential clock signals are provided by the 100lvel16 differential receiver. 2. input clock for the 100lvel16 is single-ended via j5. this signal may be 3.3 v cmos or a 2 v p-p sine wave capable of driving 50 w (r8). 3. both dac outputs from the ad9852 are routed through the two 120 mhz elliptical lp ?lters and their outputs con- nected to j3 (q) and j4 (i). 4. the board is set up for software control via the printer port connector. 5. con?gured for ad9852 operation. load the software from the cd onto the host pcs hard disk. only windows 9x/nt operating system is supported. connect a printer cable from the pc to the ad9852 evaluation board printer port connector labeled j11.
ad9852 C34C rev. 0 attach power wires to connector labeled tb1 using the screw- down terminals. this is a plastic connector that press-?ts over a 4-pin header soldered to the board. table ix below shows con- nections to each pin. dut = device under test. table ix. power requirements for dut pins avdd 3.3 v dvdd 3.3 v vcc 3.3 v ground for all dut for all dut for all other for all analog pins digital pins devices devices attach refclk there are three possibilities to choose from: 1. on-board (but optional) crystal clock oscillator, y1. insert an appropriate 3.3 v cmos clock oscillator. see that the shorting jumper at w5 is located on pins 1 and 2 (the left two pins). this routes the single-ended oscillator output to a very high speed differential receiver (the mc100lvel16), where the signal is transformed to a differential pecl output . to route the differential output signals to ad9852, two more switches must be con?gured. w9 must have a shorting jumper on pins 2 and 3 (the right two pins). to engage the differen- tial clocking mode of the ad9852 w3, pins 2 and 3 (the right two pins) must be connected with a shorting jumper. 2. external differential clock input, j5. this is actually just another single-ended input that will be routed to the mc100lvel16 for conversion to differential pecl output. this is accomplished by attaching a 2 v p-p clock or sine wave source to j5. note that this is a 50 w impedance point set by r8. the input signal will be ac- coupled and then biased to the center switching threshold of the mc 100lvel16. position the shorting jumper of w5 to pins 2 and 3 (the right two pins) to route the signal at j5 to the d ifferential receiver ic. to route the differential output signals to ad 9852, two more switches must be con?gured. w9 must have a shorting jumper on pins 2 and 3 (the right two pins). to engage the differential clocking mode of the ad9852 w3, pins 2 and 3 (the right two pins) must be connected w ith a shorting jumper. 3. external single-ended clock input, j7 . this mode bypasses the mc100lvel16 and directly drives the ad9852 with your reference clock. attach a 50 w , 2 v p-p sine source that is dc offset to 1.65 v, or a 50 w cmos-level clock source to j7. remove the shorting jumper from w5 altogether to make certain that the device (u3) is not toggling or self-oscillating. set the shorting jumper at w9 on pins 1 and 2 (the left two pins) to route the refclk signal from j7 to pin 69 of the ad9852. f inally, set the shorting jumper at w3 to pins 1 and 2 (the left two pins) to place the ad9852 in the single-ended clock mode. regardless of the origination, the signals arriving at the ad9852 are called the reference clock. if you choose to engage the on-chip refclk multiplier, this signal is the reference clock for the refclk m ultiplier and the refclk multiplier output becomes the system cl ock. if you choose to bypass the refclk multiplier, the reference clock that you have supplied is directly operating the ad9852 and is, therefore, the system clock. three-state control or switch headers w11, w12, w14, and w15 must be shorted to allow the provided software to control the ad9852 evaluation board via the printer port connector j11. if programming of the ad9852 is not to be provided by the host pc via the adi software, then headers w11, w12, w14, and w15 should be opened (shorting jumpers removed). this effectively detaches the pc interface and allows the 40-pin header, j10, to assume control without bus contention. input signals on j10 going to the ad9852 should be 3.3 v cmos logic levels. low-pass filter testing the purpose of 2-pin headers w7 and w10 (associated with j1 and j2) are to allow the two 50 w , 120 mhz ?lters to be tested during pcb assembly without interference from other circuitry attached to the ?lter inputs. normally, a shorting jumper will be attached to each header to allow the dac signals to be routed to the ?lters. if the user wishes to test the ?lters, the shorting jumpers at w7 and w10 should be removed and 50 w test signals applied at j1 and j2 inputs to the 50 w elliptic ?lters. user should refer to figure 62 and the following sections to properly position the remaining shorting jumpers. observing the un?ltered iout1 and the un?ltered iout2 dac signals this allows the viewer to observe the un?ltered dac outputs at j2 (the i signal) and j1 (the q signal). the procedure below simply routes the two 50 w terminated analog dac outputs to the bnc connectors and disconnects any other circuitry. the raw dac outputs will be a series of quantized (stepped) output levels. the default 10 ma output current will develop a 0.5 v p-p signal across the on-board 50 w termination. when connected to an external 50 w input, the dac will therefore develop 0.25 v p-p due to the double termination. 1. install shorting jumpers at w7 and w10. 2. remove shorting jumper at w16. 3. remove shorting jumper from 3-pin header w1. 4. install shorting jumper on pins 1 and 2 (bottom two pins) of 3-pin header w4. observing the filtered iout1 and the filtered iout2 this allows viewer to observe the ?ltered sine dac and control dac outputs at j4 (the sine signal) and j3 (the control dac signal). this places the 50 w (input and output z) low-pass ?lters in the i and q dac pathways to remove images and aliased harmonics and other spurious signals above the dc to approximately 120 mhz band pass. these ?lters are designed with the assumption that the system clock speed is at or near maximum (300 mhz). if the system clock utilized is much less than 300 mhz, for example, 200 mhz, unwanted dac p roducts other than the fundamental signal will be passed by the low- pass ?lters. 1. install shorting jumpers at w7 and w10. 2. install shorting jumper at w16. 3. install shorting jumper on pins 1 and 2 (bottom two pins) of 3-pin header w1. 4. install shorting jumper on pins 1 and 2 (bottom two pins) of 3-pin header w4. 5. install shorting jumper on pins 1 and 2 (top two pins) of 3- pin header w2 and w8. observing the filtered i out and the filtered i out b this allows viewer to observe only the ?ltered sine dac outputs at j4 (the true signal) and j3 (the complementary signal). this places the 120 mhz low-pass ?lters in the true
ad9852 C35C rev. 0 and complementary output paths of the sine dac to remove images and aliased h armonics and other spurious signals above approximately 120 mhz. these signals will appear as nearly pure sine waves and exactly 180 degrees out-of-phase with each other. again, if the system clock utilized is much less than 300 mhz, for example, 200 mhz, unwanted dac products other than the fundamental signal will be passed by the low-pass ?lters. 1. install shorting jumpers at w7 and w10. 2. install shorting jumper at w16. 3. install shorting jumper on pins 2 and 3 (top two pins) of 3- pin header w1. 4. install shorting jumper on pins 2 and 3 (top two pins) of 3- pin header w4. 5. install shorting jumper on pins 1 and 2 (top two pins) of 3- pin header w2 and w8. connecting the high-speed comparator in a single-ended con?guration this will allow duty cycle or pulsewidth control and requires that a dc threshold voltage be present at one of the comparator inputs. you may supply this voltage using the control dac. a 12-bit, twos-complement value is written to the control dac register that will set the iout2 output to a static dc level. allowable hexadecimal values are 7ff (maximum) to 800 (minimum) with all 0s being midscale. the i out 1 channel will continue to output a ?ltered sine wave programmed by the user. these two signals are routed to the comparator inputs using w2 and w8 3-pin header switches. the con?guration described above entitled observ ing the filtered iout1 and the fil tered iout2 must be used. follow steps 1 through 4 above and then the following step 5. 5. install shorting jumper on pins 2 and 3 (bottom two pins) of 3-pin header w2 and w8 user should elect to change the r set resistor from 3900 w to 1950 w to obtain a more robust signal at the comparator inputs. this will decrease jitter and extend comparator operating range. user can accomplish this by soldering a second 3.9 k w chip resistor in parallel with the provided r2. using the control software the control software for the ad9852/pcb evaluation board is provided on a cd. this brief set of instructions should be used in conjunction with the ad9852/pcb evaluation board schematic. several numerical entries, such as frequency and phase infor- mation, require that the enter key by pressed to register that information. 1. select the proper printer port. click the parallel port selection in the menu bar. select the port that matches your pc. if unknown, experiment by performing the following on the s elected port. with the part powered up, properly clocked and connected to the pc, select a port and go to the mode and frequency menu and click the reset dut and initialize registers button. then go to the clock and amplitude menu. o nce there, click the box next to bypass inverse sinc filter . . . a check mark will appear in the box . . . next click the button send control info to dut. if the proper port has been selected, the supply current going to the ad9852/ pcb evaluation board should drop by approximately 1/3 when the inverse sinc ?lters are bypassed. conversely, the supply current will increase approximately 1/3 when the inverse sinc ?lters are engaged. 2. normal operation of the ad9852/pcb evaluation board begins with a master reset. many of the default register values after reset are depicted in the software control panel. the reset command sets the dds output amplitude to minimum and 0 hz, 0 phase-offset as well as other states listed in the ad9852 register layout table in the preliminary data sheet. 3. the next programming block should be the reference clock and multiplier since this information is used to determine the proper 48-bit frequency tuning words that will be entered and calculated later. 4. the output amplitude defaults to the 12-bit straight binary multiplier values of the i and q multiplier registers of 000hex and no output should be seen from the dacs. user should now set both multiplier amplitudes in the output amplitude window to a substantial value, such as fffhex. you may bypass the digital multiplier by clicking the box output amplitude is always full-scale but experience has shown that doing so does not result in best sfdr it is interesting to note that best sfdr, as much as 11 db better, is obtained by routing the signal through the digital multiplier and backing off on the multiplier amplitude. for instance, fc0 hex produces less spurious signal amplitude than fff hex. its a repeatable phenomenon that should be investigated exploited for maximum sfdr (spurious-free dynamic range). 5. refer to this data sheet and evaluation board schematic to understand all the functions of the ad9852 available to the user and to gain an understanding of what the software is doing in response to programming commands. applications assistance is available for the ad9852, the ad9852/pcb evaluation board, and all other analog devices products. please call 1/800-analogd.
ad9852 C36C rev. 0 figure 62a. evaluation board schematic
ad9852 C37C rev. 0 figure 62b. evaluation board schematic
ad9852 C38C rev. 0 customer evaluation board rev c, bill of material # quantity refdes device package value 1 5 c1, c2, c35, c36, c45 chip cap 0805 2 23 c3, c7, c8, c9, c10, c11, c12, c13, c14, chip cap 0805 0.1 m f c15, c16, c17, c18, c19, c20, c22, c23, c24, c26, c27, c28, c29, c44 3 2 c4, c37 0805 0805 27 pf 4 2 c5, c38 0805 0805 47 pf 5 3 c6, c21, c25 bcaptajd tajd 10 m f 6 2 c30, c39 0805 0805 39 pf 2 c31, c40 0805 0805 22 pf 8 2 c32, c41 0805 0805 2.2 pf 9 2 c33, c42 0805 0805 12 pf 10 2 c34, c43 0805 0805 8.2 pf 11 7 j1, j2, j3, j4, j5, j6, j7 conn bnc 12 1 pcb gs02669revc 13 1 j10 40conn sam5-40 14 4 l1, l2, l3, l5 chip ind 1206 68nh 15 2 l4, l6 chip ind 1206 82nh 16 2 r1, r5 res_sm 1206 51 17 2 r2, r20 res_sm 1206 3900 18 2 r3, r7 res_sm 1206 24 19 1 r4 res_sm 1206 1300 20 3 r6, r8, r19 res_sm 1206 50 21 2 r9, r10 res_sm 1206 100 22 2 r11, r14 res_sm 1206 160 23 2 r12, r13 res_sm 1206 260 24 4 r15, r16, r17, r18 res_sm 1206 10k 25 1 rp1 rp1 sip-10p 10k 26 1 tb tb4 tb4 27 1 u1 ad9852 80lqfp 28 1 u2 74hc125a so14 29 1 u3 mc100lvel1 so8nb 30 4 u4, u5, u6, u7 74hc14 so14 31 3 u8, u9, u10 74hc574 so20wb 32 1 u11 36pinconn conn 33 7 w1, w2, w3, w4, w5, w8, w9 jump3pin sip-3p 34 8 w6, w7, w10, w11, w12, w14, w15, w16 2pinjump 2pinjump 35 1 y1 xtal cosc 36 4 pin sock amp 5-330808-6
ad9852 C39C rev. 0 figure 63. assembly drawing figure 64. top routing layer, layer 1
ad9852 C40C rev. 0 figure 65. power plane layer, layer 2 figure 66. ground plane layer, layer 3
ad9852 C41C rev. 0 figure 67. bottom routing, layer 4
ad9852 C42C rev. 0 outline dimensions dimensions shown in inches and (mm). 80-lead lqfp_ed (sq-80) 61 60 1 80 20 41 21 40 top view (pins down) pin 1 0.630 (16.00) bsc sq 0.551 (14.00) bsc sq 1 20 21 41 40 60 80 61 bottom view thermal slug 0.394 (10.00) ref sq seating plane 0.063 (1.60) max 0.004 (0.10) max coplanarity 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.0256 (0.65) bsc 7 8 3.5 8 0 8 0.008 (0.20) 0.004 (0.09) 0.015 (0.38) 0.013 (0.32) 0.009 (0.22) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) controlling dimensions in millimeters. center figures are nominal unless otherwise noted. 80-lead lqfp (st-80) top view (pins down) 1 20 21 41 40 60 61 80 0.640 (16.25) 0.620 (15.75) sq 0.553 (14.05) 0.549 (13.95) sq 0.014 (0.35) 0.010 (0.25) 0.029 (0.73) 0.022 (0.57) 0.486 (12.35) typ sq 0.063 (1.60) max 0.030 (0.75) 0.020 (0.50) seating plane 0.006 (0.15) 0.002 (0.05) 0.004 (0.10) max 0.057 (1.45) 0.053 (1.35) c3727C8C10/99 printed in u.s.a.

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